58dcb3d121
- LBC supervisor v1..v4 (linux/patches/b10b3-lbc-supervisor-v3.patch + b10/b10b3/lbc-v3-to-v4-fault-clamp.diff): CHARGING 4.20 V/450 mA -> HOLD 4.05 V after 60 min CV -> battery -> new cycle on USB insert; FAULT = VDD_MAX 4.00 V clamp - RAM tests C/B/D/D2/D3/D4 (safety timer only ends fast charge), B10B-4 actuator audit (VDD_MAX works, USB_SUSP does not), B10B-5 FAULT clamp regression, production run, warm reboot via PON reboot reason - cache = B10B-5 c3732515 (HW EDL write, readback + full partition verify), class-A persistent validation - test-only hooks/images are not part of the production kernel; images with the AP PSK are not published
30 lines
2.6 KiB
Markdown
30 lines
2.6 KiB
Markdown
# B10B3-TESTD3-RESULT — D3 kernel (VDD_MAX not rewritten at CHARGING entry): branch 2 + corrected interpretation
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Date: 2026-10-04 (UTC 2026-10-03 21:32–21:37). Image `b10/b10b3/out-d3/aurora-b10b3d3.img` 4645a7ec = Test D DTB d7bcd042 + B9C initramfs/cmdline
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(unchanged) + kernel out-b10b3d3 (v3 + `b10/b10b3/lbc-v3-to-d3.diff`, 4 lines in `lbc_enter_charging()`; .config identical; object: +1 regmap_read,
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same regmap_write count). Class A before (RTC 3 s; `pre-testD3-classA-*`, `pre-testD3-vs-preD2-diff.txt`). Operator DMM 4.067 V before power-off,
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4.058 V in B9C. RESET-held reboot → fastboot +10 s → RTC 6 s. Probe: `safety timer 8 min (TCHG_MAX 0x01)`, `INIT -> CHARGING … vbat 3992382 uV`.
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Pre-check: v3 already performs `CHG_FAILED <- 0x80` before CHARGING (`lbc_charge_restart(chg, true)`, pm8916_lbc.c:373 → :342-343) — not a difference.
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**Result: CHGR RT 01 + path 01 in 10/10 samples** (CHG_STATUS 05, CHG_CTRL a0, VDD_MAX 04, IBAT_MAX 04, TCHG 80/01, CHG_FAILED 00).
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The extra VDD_MAX write is **not** the cause. Timer test stopped as non-informative. Board left CHARGING on the D3 image.
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## Correction: the entry VBAT separates all eight runs
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| run | driver | VADC VBAT at INIT → CHARGING | CHGR RT | path |
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|---|---|---|---|---|
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| B10B-3 ram1 | v1 | 3.810 V | 20 | 02 |
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| t1 | v2 | 3.848 V | 21 | 02 |
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| t1-diag (t2) | v2 | 3.896 V | 21 | 02 |
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| Test D2 | v3 | 3.930 V | 01 | 01 |
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| Test C | v3 | 3.955 V | 01 | 01 |
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| Test B | v3 | 3.973 V | 01 | 01 |
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| Test D3 | v3+D3 | 3.992 V | 01 | 01 |
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| Test D | v3 | 3.999 V | 01 | 01 |
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Every FAST_CHG_ON entry was ≤ 3.896 V, every non-FAST entry ≥ 3.930 V. With D3 the v3 register-write sequence equals v2's, and v2 vs v3
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probe timing/order is the same (INIT after configure in both dmesgs). **The TESTD2 conclusion "low VBAT does not restore fast charge in v3" was
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wrong**: 3.930 V was simply above a threshold that lies between 3.896 and 3.930 V (VADC at INIT, SBL-charge-loaded).
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Best-supported hypothesis: the LBC enters its fast-charge state (FAST_CHG_ON, path 02) only when VBAT is below the VBAT_DET comparator at the
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restart; above it, it charges in a state without FAST_CHG_ON (path 01). This matches the stock driver, which always sets the VBAT_DET override
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(COMP_OVR1 = 0x2, "enable charging irrespective of VBAT above VBAT_DET", LBC:1660–1669) — we keep COMP_OVR1 = 00. Not proven; driver/version
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is confounded with VBAT in the old runs only through v1/v2, and D3 removes the write difference.
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Logs: d3r1/, d3r1-*.txt, UART logs/uart/b10b3d3-ram1-20261004-003317.log (480s), kernel build log build-b10b3d3-kernel.log.
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