58dcb3d121
- LBC supervisor v1..v4 (linux/patches/b10b3-lbc-supervisor-v3.patch + b10/b10b3/lbc-v3-to-v4-fault-clamp.diff): CHARGING 4.20 V/450 mA -> HOLD 4.05 V after 60 min CV -> battery -> new cycle on USB insert; FAULT = VDD_MAX 4.00 V clamp - RAM tests C/B/D/D2/D3/D4 (safety timer only ends fast charge), B10B-4 actuator audit (VDD_MAX works, USB_SUSP does not), B10B-5 FAULT clamp regression, production run, warm reboot via PON reboot reason - cache = B10B-5 c3732515 (HW EDL write, readback + full partition verify), class-A persistent validation - test-only hooks/images are not part of the production kernel; images with the AP PSK are not published
63 lines
6.1 KiB
Markdown
63 lines
6.1 KiB
Markdown
# B10B3-RESULT — production-profile final RAM run (DESIGN 8.7) and B10B-3 criteria
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Date: 2026-10-04 (UTC 01:28 – 11:46). **Status: B10 charging logic: RAM VALIDATED** (criterion 7 with a scope limitation, see below).
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Image `b10/b10b3/out-p/aurora-b10b3p.img` 8bcd613e = v3 kernel 1164b1c7 (same as Test C/B/D, **no D3 change**) + B9C initramfs/cmdline +
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DTB `linux/dts/msm8916-jz08-aurora-b10b3p.dts` (= production `msm8916-jz08-aurora-b10b3.dts`, only the model string differs; decoded:
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charge 4200000 → VDD_MAX 08, HOLD 4050000 → 02, full-min 4150000, CV 60 min, timer 512 min → TCHG 80/7f, fast-charge-safe-current 500000 → IBAT_MAX 04).
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RAM boot only; aboot/cache/eMMC untouched; COMP_OVR not touched; no manual charger-register writes.
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## Run p1 (t from probe 0.927 s; monitor 30 s, 1159 samples; logs `p1/`, `p1-*.txt`, `p1-mon-board-final.txt`, UART `logs/uart/b10b3p-ram1-20261004-042944.log` on 480s)
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- Class A before (RTC 3 s; `pre-prod-classA-check.txt`, `pre-prod-classA-dump.txt`, `pre-prod-vs-preD3-diff.txt`: ADC/BMS/RTC only). B9C DMM 4.074 V,
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USB 0.41 A. RESET-held reboot → fastboot → boot (stage-3 again, RTC 5 s; driver programs everything at probe).
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Note: the first monitor starter misfired on one lost ping (pushed the monitor to B9C, stopped; `p1-actions-misfire.txt`); starter now waits for fastboot.
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- t 0: `INIT -> CHARGING (probe, usb present)`, VBAT 4.011 V: VDD_MAX 08, IBAT_MAX 04, CHG_CTRL a0, TCHG 80/7f, BOOT_DONE 80, path 01 (non-fast entry, as
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expected for a probe after SBL above ≈ 3.93 V), USB 0.41 A.
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- CC → CV at 4.20 V (first CV sample t ≈ 3208 s, VBAT ≈ 4.18 V under charge) → **CHARGING → HOLD at t = 6666.5 s** after 60 min CV (vbat 4.183 V),
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only VDD_MAX 08 → 02.
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- HOLD phase 1: 4.18 → 4.05 V (≈ 1.4 mV/min, USBIN 5.017 V = board on battery). **Shelf from t ≈ 12100 s: VADC 4.033–4.056 V over 743 samples
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(≈ 6.3 h), never rising**; USBIN 4.95–5.00 V (USB carries the board). Operator on the shelf: **USB 0.1 A, DMM 4.035 V**.
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- usbpull3 (heartbeat on UART): DMM 4.035 → 4.009 V at the pull → 4.007 V; 44 beats, max gap 5.02 s, no SBL/boot; display and Wi-Fi kept working
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(operator). `HOLD -> NO_USB` t 34512 s (no writes). Re-insert after ≈ 105 s: `NO_USB -> CHARGING (usb inserted)` t 34618 s → VDD_MAX 08, IBAT 04,
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CHG_CTRL a0, CHG_FAILED 00, FAST + path 02; DMM 4.003 → 4.10 V, USB 0.4 A.
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- Whole run: 0 ALERT, CHG_FAILED 00 in all samples, no FAULT, n_latch 0, PMIC max 45.7 °C (CC), 33–43.6 °C on the shelf. eMMC writes 0.
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LTE START OK 73.6 s, ping 4/4 (boot) and 4/4 (t ≈ 34400 s); Wi-Fi AP enabled 77.1 s; MSS + WCNSS running; DRM SPI panel enabled, backlight on; NCM throughout.
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- The run was ended at t ≈ 34935 s (CHARGING after the re-insert) by the warm-reboot feasibility test (B10B3-RBL1-RESULT.md).
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## Criterion 7 — warm reboot: PASS with scope limitation (operator decision, variant B)
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Confirmed (B10B3-RBL1-RESULT.md):
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- `reboot(RESTART2, "bootloader")` (`b10/b10b3/rbl/reboot-bootloader`) puts lk1st into fastboot without a physical RESET (PON 0x88F[7:2] = 2,
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lk1st `USE_PON_REBOOT_REG`); lk1st fastboot data transfer needs one USB replug after a Linux reboot (lk1st quirk).
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- No stage-3 PMIC reset (POFF_REASON2 0x80D 00); RTC continuous (34940 → 36836 s); PON_REASON1 0x808 = 11 (hard reset via PS_HOLD, POFF_REASON1 02).
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- After the warm reboot part of the charger configuration is re-initialised to the SBL values: IBAT_MAX 00, IBAT_SAFE 0a, CHG_CTRL 90, TCHG_MAX 1d
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(BOOT_DONE 80, VDD_SAFE 08, 0x105B 09, 0x10EE 00 unchanged; VDD_MAX was 08 before and after).
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- The production driver at probe programs the required CHARGING state from exactly this SBL-default state — VDD_MAX 4.20 V (08), IBAT_MAX 450 mA (04),
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CHG_CTRL 0xA0, safety timer 512 min (80/7f), BOOT_DONE 1 — and charging/USB path come up normally (every probe of this run series started from
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SBL-default charger registers; p1 probe above).
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Scope limitation (recorded, not hidden):
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- Preservation of VDD_MAX = 4.05 V from HOLD through a warm reboot was **not** tested (no 2-h HOLD re-run, variant A not done).
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- This is **not a production requirement**: after any reboot the design deliberately starts a new charge cycle and programs VDD_MAX = 4.20 V anyway.
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- The earlier statement "charger settings survive class-B/warm reboots" is **withdrawn as wrong**. Correct model:
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`warm reboot → SBL partially re-initialises the charger → the driver always re-programs the production configuration`.
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## B10B-3 criteria (final RAM run)
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| # | criterion | result |
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| 1 | CHARGING → CV → HOLD automatically | **PASS** (HOLD at t 6666.5 s after 60 min CV) |
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| 2 | HOLD: VDD_MAX → 4.05 V, VBAT does not rise | **PASS** (VDD_MAX 02; shelf 4.033–4.056 V for ≈ 6.3 h) |
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| 3 | no 00+01 latch, CHG_FAILED, FAULT/ALERT | **PASS** (n_latch 0, CHG_FAILED 00, 0 ALERT, no FAULT) |
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| 4 | USB carries the system in HOLD | **PASS** (USB 0.1 A on the shelf, USBIN sag, VBAT flat) |
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| 5 | HOLD → USB unplug → battery without reset | **PASS** (usbpull3; also usbpull2 in Test D4) |
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| 6 | USB insert → correct recovery | **PASS** (NO_USB → CHARGING, production registers, FAST + path 02) |
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| 7 | warm reboot → driver restores the production state | **PASS with scope limitation** (see above) |
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| 8 | LTE / Wi-Fi / NCM / display alive | **PASS** |
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| 9 | eMMC writes = 0 | **PASS** |
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| 10 | PMIC temperature safe | **PASS** (max 45.7 °C) |
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## Open items (not blockers for the RAM validation)
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- No verified software emergency stop (CHG_EN = 0 does not stop the LBC; DESIGN 8.4/1) — FAULT remains logical only.
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- Safety timer is not a charge-stop protection (Test D4); charging is bounded by VDD_MAX regulation + HOLD logic.
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- FAST vs non-fast entry condition at probe (≈ 3.90–3.93 V threshold after SBL; FAST at 4.02 V after a USB insert) not fully explained.
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- Thermal margin with extra CPU load (Test C: 57.9 °C) — derating not implemented (out of scope now).
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- lk1st fastboot needs a USB replug after a software reboot (test-harness only).
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- Cosmetic: debugfs `cv_s` keeps counting in HOLD; monitor `load=` field broken.
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- Persistent (cache) integration: separate GO.
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