58dcb3d121
- LBC supervisor v1..v4 (linux/patches/b10b3-lbc-supervisor-v3.patch + b10/b10b3/lbc-v3-to-v4-fault-clamp.diff): CHARGING 4.20 V/450 mA -> HOLD 4.05 V after 60 min CV -> battery -> new cycle on USB insert; FAULT = VDD_MAX 4.00 V clamp - RAM tests C/B/D/D2/D3/D4 (safety timer only ends fast charge), B10B-4 actuator audit (VDD_MAX works, USB_SUSP does not), B10B-5 FAULT clamp regression, production run, warm reboot via PON reboot reason - cache = B10B-5 c3732515 (HW EDL write, readback + full partition verify), class-A persistent validation - test-only hooks/images are not part of the production kernel; images with the AP PSK are not published
1.9 KiB
B10B3-T1DIAG-RESULT — can the LBC still reach FAST_CHG_ON + path 02? (5-min diagnostic, RAM only)
Date: 2026-10-04 (UTC 2026-10-03 20:38–20:45). Result: YES. Historic B10B-3T image b10/b10b3/out-t/aurora-b10b3t.img dfe2fae6 (= t1: v2 driver,
DTB 4.00 V / recharge 3.94 V / 450 mA / 512 min), no manual register writes, eMMC w=0.
Preparation: B9C on battery after a USB pull survived (usbpull1, see t1pre-actions.txt); discharge on B9C with 4×yes to DMM 3.902 V at rest;
class A (RTC 3 s; pre-t1diag-classA-check.txt, pre-t1diag-classA-dump.txt, pre-t1diag-vs-preD-diff.txt: only 0x100B 43→03, 0x1010 01→00
- ADC/BMS/RTC). Pre-boot DMM 3.988 V, USB 0.403 A (SBL charge). RESET-held
reboot→ fastboot +12 s →fastboot boot20:38:50 UTC; RTC 4 s. Probe:safety timer 512 min (TCHG_MAX 0x7f),supervisor INIT -> CHARGING (probe, usb present), vbat 3896340 uV.
Monitor 5 s, 62 samples, uptime 15.6–329 s: CHGR RT 21 (FAST_CHG_ON) + path 02 in 62/62, CHG_STATUS 05, CHG_CTRL a0, VDD_MAX 00, IBAT_MAX 04,
TCHG 80/7f, CHG_FAILED 00, no ALERT. VADC VBAT 3.979–4.003 V, PMIC max 48.7 °C, USBIN 4.895 V (current flowing).
End dump (t2-end-dump.txt, up 361 s) vs Test D end dump (t2-vs-d1-charger-diff.txt): in all charger blocks only 0x1010 21↔01, 0x1308 02↔01 and the
timer value 0x1061 differ → same configuration, different FSM state.
Interpretation: the "path 01, no FAST_CHG_ON, still charging" state of Tests B/C/D is not a property of the board/battery; v2 at VBAT ≈ 3.90 V reaches FAST_CHG_ON + path 02. Not yet separated: v3 entry sequence (BOOT_DONE update + VDD_MAX write right before the 0x21 → 0xa0 edge, supervisor start after probe, VADC VBAT_SNS use) vs the entry VBAT (v3 runs entered at 3.955–3.999 V, v1/v2 at 3.85–3.90 V). Board left CHARGING on the B10B-3T image (VDD 4.00 V, timer 512 min). Logs: t2/, t2-*.txt, UART logs/uart/b10b3t-ram2-20261003-233621.log (480s).