58dcb3d121
- LBC supervisor v1..v4 (linux/patches/b10b3-lbc-supervisor-v3.patch + b10/b10b3/lbc-v3-to-v4-fault-clamp.diff): CHARGING 4.20 V/450 mA -> HOLD 4.05 V after 60 min CV -> battery -> new cycle on USB insert; FAULT = VDD_MAX 4.00 V clamp - RAM tests C/B/D/D2/D3/D4 (safety timer only ends fast charge), B10B-4 actuator audit (VDD_MAX works, USB_SUSP does not), B10B-5 FAULT clamp regression, production run, warm reboot via PON reboot reason - cache = B10B-5 c3732515 (HW EDL write, readback + full partition verify), class-A persistent validation - test-only hooks/images are not part of the production kernel; images with the AP PSK are not published
26 lines
2.6 KiB
Markdown
26 lines
2.6 KiB
Markdown
# B10B3-TESTD2-RESULT — v3 (unchanged Test D image) at low entry VBAT: branch 2
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Date: 2026-10-04 (UTC 2026-10-03 20:55–21:00). Image `b10/b10b3/out-d/aurora-b10b3d.img` 43739e55 (unchanged), no manual writes, eMMC w=0.
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Class A before (RTC 3 s; `pre-testD2-classA-check.txt`, `pre-testD2-classA-dump.txt`, `pre-testD2-vs-pre-t1diag-diff.txt`: ADC/BMS/RTC only).
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Operator: before class A DMM 3.8966 V / 0.23 A; B9C DMM 3.991 V, USB 0.415 A. RESET-held reboot → fastboot +5 s → boot 20:57:52 UTC, RTC 6 s.
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Probe: `safety timer 8 min (TCHG_MAX 0x01)`, `supervisor v3 … charge 4100000`, `INIT -> CHARGING (probe, usb present), vbat 3929739 uV`.
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**Result: CHGR RT 01 + path 01 in every sample** (11/11 to uptime 65 s, 15 total), CHG_STATUS 05, CHG_CTRL a0, VDD_MAX 04, IBAT_MAX 04,
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TCHG 80/01, CHG_FAILED 00, VADC VBAT 4.02 V (under charge), PMIC 46.7 °C → **FAST_CHG_ON = 0 although the entry VBAT (3.930 V) is as low as
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in the v2 run (3.896 V, FAST_CHG_ON = 1).** Timer test stopped as non-informative (branch 2). Low VBAT does not restore fast charge in v3.
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Charger blocks t2 (v2, FAST) vs d2 (v3) end dumps (`t2-vs-d2-charger-diff.txt`): 0x1009/0x1010/0x1308 (state) and the configured levels
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0x1040 (4.00 vs 4.10 V), 0x1061 (timer) only.
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## v2 vs v3 sequence (sources: v2 = linux/patches/b10b3-lbc-recharge-supervisor.patch on upstream; v2 + b10/b10b3/lbc-v2-to-v3.diff == built v3, verified by cmp)
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Probe (identical in both): VDD_SAFE, IBAT_SAFE, TCHG_MAX_EN 0 → TCHG_MAX → EN 0x80, configure(probe): VDD_MAX, IBAT_MAX, CHG_CTRL = 0xa0.
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Supervisor INIT → CHARGING:
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- v2: `lbc_charge_restart(chg, true)`: CHG_FAILED ← 0x80, CHG_CTRL[7,0] ← FORCE_BATT_ON (0x21), 20 ms, ← CHG_EN (0xa0).
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- v3: `lbc_enter_charging()`: BOOT_DONE update_bits (no write: lk1st fastboot already set 0x80 — v2 never writes it and t2 shows 0x80),
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**VDD_MAX write (same value as at probe)**, IBAT_MAX read (no write, equal), then the same `lbc_charge_restart(chg, true)`.
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DTB t vs d: only the levels (VDD 4.00 vs 4.10 V), the timer and the v3 HOLD properties. VDD level is not the cause (v1 ram1 at 4.20 V had FAST).
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→ **The only effective register-write difference before the edge is the extra VDD_MAX write immediately before the 0x21 → 0xa0 restart.**
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This is the prime suspect, not yet proven.
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Board left CHARGING on the Test D image. Logs: d2/, d2-*.txt, UART logs/uart/b10b3d-ram2-20261003-235644.log (480s).
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**Correction (2026-10-04, after D3, see B10B3-TESTD3-RESULT.md):** the conclusion above that low VBAT does not restore fast charge is withdrawn —
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3.930 V was above the threshold (FAST runs entered at ≤ 3.896 V). The "VDD_MAX write" suspect was tested in D3 and is not the cause.
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