58dcb3d121
- LBC supervisor v1..v4 (linux/patches/b10b3-lbc-supervisor-v3.patch + b10/b10b3/lbc-v3-to-v4-fault-clamp.diff): CHARGING 4.20 V/450 mA -> HOLD 4.05 V after 60 min CV -> battery -> new cycle on USB insert; FAULT = VDD_MAX 4.00 V clamp - RAM tests C/B/D/D2/D3/D4 (safety timer only ends fast charge), B10B-4 actuator audit (VDD_MAX works, USB_SUSP does not), B10B-5 FAULT clamp regression, production run, warm reboot via PON reboot reason - cache = B10B-5 c3732515 (HW EDL write, readback + full partition verify), class-A persistent validation - test-only hooks/images are not part of the production kernel; images with the AP PSK are not published
52 lines
5 KiB
Markdown
52 lines
5 KiB
Markdown
# B10B3-TESTC-RESULT — HOLD mechanism (v3 supervisor, RAM only)
|
||
|
||
Date: 2026-10-03. **Verdict: PASS** (with the observations below). Image `b10/b10b3/out-c/aurora-b10b3c.img` 5ff9dec0 (test-only DTB:
|
||
charge 4.10 V, HOLD 4.00 V, full-min 4.05 V, CV 5 min, IBAT_MAX 450 mA, timer 512 min). aboot/cache untouched, eMMC writes = 0, no manual PMIC writes.
|
||
|
||
## Bench preparation
|
||
Class-A reset (USB out, battery out ≈2 min 12 s, battery, USB, no RESET) → B9C, RTC 3 s; read-only snapshot = SBL defaults
|
||
(`pre-testC-classA-check.txt`: VDD_MAX 08, IBAT_MAX 00, IBAT_SAFE 0a, CHG_CTRL 90, TCHG 80/1d, 0x105B 09, 0x10EE 00, BOOT_DONE 00, charging 05/02).
|
||
Then warm reboot with RESET held (second attempt; first one missed) → lk1st fastboot → `fastboot boot` Test C at 18:20:50 (class B after the clean class A).
|
||
|
||
## After probe (`c1-probe-state.txt`)
|
||
`safety timer 512 min (TCHG_MAX 0x7f), enabled`; `supervisor v3: charge 4100000, hold 4000000, full-min 4050000, cv 5 min, IBAT_MAX code 4`;
|
||
INIT → CHARGING at 3.955 V. Registers: BOOT_DONE 80, VDD_MAX 04 (4.10 V), IBAT_MAX 04 (450 mA), TCHG_MAX_EN/TCHG_MAX 80/7f, CHG_CTRL a0,
|
||
CHG_FAILED 00, USB RT 03 (valid). VADC/BMS/PMIC temp working. LTE START OK 73.7 s, Wi-Fi AP enabled 78.1 s, NCM ok.
|
||
|
||
## Timeline (`c1-mon.txt`, 30 s samples; operator: USB meter + DMM soldered to VBAT/GND)
|
||
| phase | uptime | VADC VBAT | USB meter | registers |
|
||
|---|---|---|---|---|
|
||
| CHARGING (CC) | 0–≈1780 s | 3.955 → 4.10 V | 0.358 A steady | CHG_STATUS 05, CHGR RT 01, **USB path 01** (not 02!), VDD_MAX 04 |
|
||
| CHARGING (CV at 4.10 V) | ≈1780–2059 s | 4.077–4.100 V | — | CV bit seen (03/05 interleave), supervisor cv_s 0 → 328 s |
|
||
| **→ HOLD** | **2059 s** | 4.083 V | — | dmesg `CHARGING -> HOLD (CV time reached, VDD_MAX -> hold level)`; **only VDD_MAX 04 → 00** |
|
||
| HOLD phase 1 | 2059–≈3250 s | 4.022 (immediate step −60 mV) → 4.0137 → ≈4.00 V, ≈−1.4 mV/min | **≈0.01 A** | CHG_STATUS 03, CHG_CTRL a0, PMIC 36.7 → 33.8 °C |
|
||
| HOLD phase 2 (no extra load) | ≈3250–3850 s | 4.000–4.008 V stable | 0.03–0.08 A | 03, a0, 00 |
|
||
| load step 4×CPU (operator request) | ≈3860–4030 s | 3.980–4.001 V | **0.2–0.3 A** (DMM 3.983 / 3.972 V) | PMIC rose to 57.9 °C → load stopped early at 19:27:51 |
|
||
| HOLD phase 2 after load | 4040–4372+ s | **4.0014–4.0022 V (±1 mV, 11+ samples)** | 0.07 A, peaks 0.1 A (DMM 3.991 V, "battery stands") | 03, a0, 00; PMIC 37.3 °C |
|
||
|
||
## Checks
|
||
- Automatic CHARGING → HOLD: PASS (5 min CV with VBAT ≥ 4.05 V, single transition, n_hold 1).
|
||
- Only the new VDD_MAX was written: PASS. Full diff vs the class-A baseline (CHGR/BAT_IF/USB/MISC): config changes exactly the expected ones
|
||
(0x1040 08→00 HOLD, 0x1044 00→04, 0x1045 0a→04, 0x1049 90→a0, 0x1061 1d→7f, 0x1642 00→80 [+0x1643 0b]); status-only 0x1009/0x100b/0x1010.
|
||
TCHG_MAX_EN 80 (timer enabled), CHG_FAILED 00, 0x105B 09, 0x10EE 00 unchanged.
|
||
- VBAT falls to 4.00 V after HOLD: PASS (phase 1, −1.4 mV/min; VBAT never rose after HOLD).
|
||
- USB carries the system on the shelf: PASS — VBAT stable at 4.000–4.002 V for > 10 min with USB input 0.03–0.1 A; a 4×CPU load step was taken
|
||
from USB (0.2–0.3 A) with VBAT staying at the shelf.
|
||
- 00/01 latch: did not occur (n_latch 0) → the HOLD restart path is implemented but not exercised.
|
||
- LTE ping 5/5 via wwan0, Wi-Fi AP aurora-b8f up (Pronto running, 0 crashes), NCM/UDC configured, display (fb0 panel-mipi-dbid, backlight on): PASS.
|
||
- eMMC writes = 0 (mmcblk0 write I/Os 0 in every dump).
|
||
- PMIC temperature: max 48 °C while charging; **57.9 °C during the extra CPU-load step** (CPU 73 °C next to it + ≈0.3 A through the linear
|
||
charger) — close to the 60 °C abort level; load was stopped early. No ALERT in the logged 30-s samples.
|
||
|
||
## Observations / corrections
|
||
1. **USB path 0x1308 = 01 does not mean "not charging":** CC charging at 0.358 A ran with 0x1308 = 01 and CHGR RT 01 (no FAST_CHG_ON).
|
||
Only the pair CHG_STATUS 00 + path 01 is the latch; the supervisor already uses the pair.
|
||
2. **Board idle consumption on USB is ≈0.03–0.1 A, not 0.15–0.20 A.** The earlier 0.15–0.20 A figures were measured while charging (board +
|
||
battery). Corrected expectation for HOLD phase 2: USB input ≈ board load (≈0.03–0.1 A idle, rising with load), VBAT flat at the shelf.
|
||
3. HOLD phase 1 indeed has ≈0.01 A USB input while VBAT > shelf (VPH = VBAT, no power path) — as predicted; phase 2 resumes USB supply.
|
||
4. Cosmetic: the debugfs `cv_s` keeps counting in HOLD (cv_since not cleared on the transition) — no functional effect; fix in the next build.
|
||
5. HOLD-phase durations at the test levels: phase 1 ≈ 20 min for 80 mV; production (4.20 → 4.05 V) will take longer (≈150 mV).
|
||
|
||
## State after the test
|
||
Board left in HOLD on the Test C RAM image (VDD_MAX 4.00 V, timer 512 min enabled, USB carrying the load). Monitor and pull stopped.
|
||
LBC registers written by the test survive warm reboots → a class-A reset is required before the next test. Test B not started (needs GO).
|