58dcb3d121
- LBC supervisor v1..v4 (linux/patches/b10b3-lbc-supervisor-v3.patch + b10/b10b3/lbc-v3-to-v4-fault-clamp.diff): CHARGING 4.20 V/450 mA -> HOLD 4.05 V after 60 min CV -> battery -> new cycle on USB insert; FAULT = VDD_MAX 4.00 V clamp - RAM tests C/B/D/D2/D3/D4 (safety timer only ends fast charge), B10B-4 actuator audit (VDD_MAX works, USB_SUSP does not), B10B-5 FAULT clamp regression, production run, warm reboot via PON reboot reason - cache = B10B-5 c3732515 (HW EDL write, readback + full partition verify), class-A persistent validation - test-only hooks/images are not part of the production kernel; images with the AP PSK are not published
43 lines
5.1 KiB
Markdown
43 lines
5.1 KiB
Markdown
# B10B4-RESULT — emergency charge actuator audit (RAM only)
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Date: 2026-10-04 (UTC ≈ 12:51–14:00). Image `b10/b10b3/out-b4/aurora-b10b4.img` eeff6820 (TEST-ONLY kernel 7.2.7-aurora-b10b4-debug,
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debugfs `pm8916_lbc/b10b4`, production DTB values; review `B10B4-HOOK-REVIEW.md`). No flash; production artifacts and the cache candidate
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86869061 unchanged. RESET-held boot (stage-3, RTC 6 s); probe `INIT -> CHARGING` at 4.097 V; hook banner present; b10b4 mode `--w-------`.
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Logs: `b4r1/` (boot, snapshot, UART on 480s `logs/uart/b10b4-ram1-20261004-154537.log`), `b4r1/board/` (b4-t*.log fast logs 1 s ×12 then 5 s ×10,
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discharge log, monitor log, dmesg), `b4r1-actions.txt` (operator readings), `b4-base1.txt`.
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**No direct battery-current sensor: the USB meter is the total board input; VADC USBIN sag and VBAT steps are indirect.**
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## Hook negative tests
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`foo 1`, `vdd 9`, `ibat 5`, `susp 2`, `vdd 1 2`, `vdd`, `vdd x`, `addr 0x1040 0` → all rejected (rc 1 / -EINVAL), 0 hook log lines, registers unchanged.
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## Precondition discharge (operator GO)
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USB off at uptime 320 s (`CHARGING -> NO_USB`, no writes), 4×yes until VADC ≤ 3.995 V ×3 (loaded) → LOAD-STOP 2077.6 s (29.3 min), PMIC max 52.7 °C,
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heartbeat continuous, no reset. VADC at re-insert 4.085 V (target window 4.04–4.07 V missed by ≈ 15 mV — DMM/VADC offset larger than assumed;
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still > 4.00 V as required for Test 2). Re-insert → `NO_USB -> CHARGING`, FAST (RT 21, path 02).
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## Baseline before each test
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CHARGING, FAST (RT 21, path 02), CHG_STATUS 05, VDD_MAX 08, IBAT_MAX 04, CHG_CTRL a0, CHG_FAILED 00, USB_SUSP 00, USB_RT 03; VADC VBAT ≈ 4.15 V
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(under charge), USBIN 4.88 V; PMIC 45–50 °C; USB meter 0.41–0.47 A; LTE ping OK, MSS/WCNSS running, backlight on.
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Restore before Test 3 needed a USB replug (FAST is not re-entered by `vdd 8`); the first operator "replug" was not seen by the board, the second
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(≥ 10 s) was (`NO_USB` 3663.5 s → `CHARGING` 3720.5 s).
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## Results
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| actuator | USB input before → after | VBAT slope after the action | USB path / RT | supervisor reaction | reversible | board stable | verdict |
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|---|---|---|---|---|---|---|---|
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| **susp 1** (0x1347 b0) | 0.46 → **0.41 A**; USBIN sag unchanged (4.884 V) | **+2.0 mV/min** (charging continues; +5 mV over ≈ 3 min) | 02→01, RT 21→00; USB_RT 03 stays valid | none (stays CHARGING, no writes) | yes — `susp 0` → FAST back instantly (RT 21, path 02), no driver action | yes (display on) | **NOT an actuator** (only ends FAST; input stays) |
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| **vdd 0** (VDD_MAX 4.20→4.00 V, VBAT 4.155 V) | ≈ 0.46 → **0.000 A** (+5 s and +60 s); USBIN 4.883 → **5.024 V** (no sag) | immediate step 4.153 → 4.093 V (IR drop of the charge current gone), then **−11 mV/min** (board on battery; includes relaxation) | 02→01, RT 21→01, CHG_STATUS 05→03 | none (stays CHARGING, no writes) | yes — `vdd 8` → charging resumes at once (USBIN sag back, VBAT +), but **in the non-fast state** (path 01); FAST needs a USB re-insert | yes; PMIC 49 → 37 °C during the stop (no charger dissipation) | **WORKS as charge stop while VBAT > 4.00 V** |
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| **ibat 0** (IBAT_MAX 450→90 mA) | ≈ 0.41 → reported "0.8" at +5/+60 s (**to confirm: 0.08 A expected**); USBIN 4.881 → 4.992 V (partial sag) | step 4.155 → 4.103 V, then ≈ −10 mV/min (90 mA ≈ board load; includes relaxation) | stays 02, RT 21 (FAST kept) | none | yes — `ibat 4` → full current at once, FAST kept | yes; PMIC 46 → 39.6 °C | **derating, not a stop** (90 mA still flows; net battery ≈ 0 only because of the board load) |
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| combination (Test 4) | not run — Test 2 already gave a working actuator (per the GO rule) | | | | | | — |
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CHG_FAILED 00 in all 144 fast-log samples and all 133 monitor samples; monitor ALERTs only the expected ALERT-VDDMAX (Test 2 window) and ALERT-IBAT (Test 3 window); no reset
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(uptime continuous, heartbeat), eMMC writes 0, PMIC max 49.2 °C in the test windows. Final state: FAST baseline restored (VDD_MAX 08, IBAT_MAX 04,
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CHG_CTRL a0, USB_SUSP 00, path 02, RT 21), LTE ping OK, MSS/WCNSS running, backlight on; board left CHARGING on the test image.
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## Selection
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- **Primary FAULT actuator: VDD_MAX → 0x00 (4.00 V).** Input current to ≈ 0 within the first sample (< 1 s), VBAT steps down and falls, board keeps
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running from the battery, no latch, reversible, no supervisor interference. Same mechanism as HOLD phase 1 (already validated). Limitation:
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it stops charging only while VBAT > 4.00 V; below 4.00 V the charger would still charge **up to 4.00 V** (a safe cap, not a stop).
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For the defined FAULT causes (OVP > 4.25 V; a stuck CHARGING high in the cell) VBAT is far above 4.00 V, so it acts as a stop.
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- **Hard emergency actuator: none verified that stops charging at any VBAT.** USB_SUSP does not cut the input. Best available = VDD_MAX 0x00 +
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IBAT_MAX 0x00 (cap 4.00 V at ≤ 90 mA) — not tested as a combination (Test 4 skipped per rule); would need its own GO if required below 4.00 V.
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- **Derating actuator: IBAT_MAX** (0x00 = 90 mA; FAST kept; immediately reversible) — candidate for the PMIC-temperature derating noted in 8.10.
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Nothing integrated into the production driver; no persistent candidate rebuilt.
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